上海配资

65nm/55nm

65nm/55nm

Technology Overview

The 65nm/55nm logic technology combines improved performance and reduced power consumption with increased design possibilities and cost efficiencies. The 65nm/55nm logic process standard offerings include Low Leakage (LL) and Ultra Low Power (ULP) platforms. Both LL and ULP processes offer three threshold voltage core devices and 1.8V, 2.5V and/or 3.3V I/O options to provide a flexible design platform. Design rules, specifications, and SPICE models are available for 65nm/55nm. Critical IPs are ready for 55nm LL/ULP and 65nm LL.

Features

上海配资Logic Standard Offering

Standard Offering

55LL

65LL

上海配资Core Device

(1.2V)

ULL

HVt

SVt

LVt

 

 

I/O Device

1.8V

2.5V

3.3V

上海配资2.5V OD 3.3V

2.5V UD 1.8V

 

Memory

SP HD SRAM

SP HP SRAM

DP HD SRAM

DP HP SRAM

0.425μ㎡

0.502μ㎡

0.789μ㎡

0.938μ㎡

0.525μ㎡

0.620μ㎡

0.974μ㎡

1.158μ㎡

 

Application Usage

上海配资SMIC 55nm LL process targets a wide range of applications, such as mobile devices, computers, IoT and wearables.

  • 上海配资 Mobile Devices

  • 上海配资 IoT and Wearables

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